The invention relates to a signal processing device and a signal processing method which perform maximum likelihood decoding of convolutionally coded data, and in particular to a signal processing device and a signal processing method which detect the data rate of transmitted data.
In the prior art, data is transmitted at a predetermined data rate among a plurality of prepared data rates, and the data rate has been detected on the receiving side. FIG. 1 shows an example of configuration of a communication system which transmits and receives data at an arbitrary data rate among a plurality of predetermined data rates, and which includes a conventional reception device 3.
The transmission device 1 transmits convolutionally coded data at an arbitrary data rate among a plurality of predetermined data rates to the reception device 3, via the communication path 2.
FIG. 2 shows an example of the transport format of data here being transmitted and received. In this format, a CRC (Cyclic Redundancy Check) code is appended to the data stream; however because the length of the data stream varies according to the data rate, the tail bit (final bit of the CRC) nend differs depending on the data rate. In the following explanation, the final bit of the CRC shall be called the tail bit nend.
For example, when as shown in FIG. 2 there exist four data rates R1, R2, R3, R4 (where data rate R1<data rate R2<data rate R3<data rate R4), the tail bits nend for each of the data rates R1 to R4 become the E1st bit ((a) in FIG. 2), the E2nd bit ((b) in FIG. 2), the E3rd bit ((c) in FIG. 2), or the E4th bit ((d) in FIG. 2), counting from the leading bit S.
The interval from the E1st, E2nd and E3rd bits which are the tail bits nend for data rates R1 to R3 in transport formats at the data rates R1 to R3, until the bit equivalent to the E4th bit which is the tail bit nend for data rate R4, is an empty interval containing no data.
The reception device 3 performs Viterbi decoding of data (FIG. 2) transmitted from the transmission device 1 via the communication path 2. The reception device 3 also detects the data rate of the received data, and outputs decoded data, at the detected data rate, to a data processing device (not shown) connected to the reception device.
Next, the configuration of the transmission device 1 and reception device 3 shown in FIG. 1 is explained.
The transmission device 1 has a CRC (Cyclic Redundancy Check) encoder 11, convolutional coding portion 12, and modulation portion 13. The CRC encoder 11 appends to the data stream a CRC parity bit for data to be transmitted, and supplies the result to the convolutional coding portion 12.
The convolutional coding portion 12 performs convolutional coding of the data from the CRC encoder 11, and supplies the result to the modulation portion 13. The modulation portion 13 modulates the data from the convolutional coding portion 12, and transmits the result to the reception device 3 via the communication path 2.
The reception device 3 has a demodulation portion 31, Viterbi decoding portion 32, CRC decoder 33, and data rate detection portion 34. The demodulation portion 31 demodulates the received data, and supplies the result to the Viterbi decoding portion 32.
The Viterbi decoding portion 32 is controlled by the data rate detection portion 34, and performs Viterbi decoding of data from the demodulation portion 31, supplying the data thus obtained (decoded data) to the CRC decoder 33.
The Viterbi decoding portion 32 supplies to the data rate detection portion 34 the maximum path metric, minimum path metric, and zero-state path metric calculated at this time.
The Viterbi decoding portion 32 outputs the decoded data obtained as a result of Viterbi decoding to a device, not shown, at the data rate detected by the data rate detection portion 34.
The CRC decoding portion 33 is controlled by the data rate detection portion 34, and performs a CRC check of the data from the Viterbi decoding portion 32, supplying the check result to the data rate detection portion 34.
The data rate detection portion 34 controls the Viterbi decoding portion 32 and CRC decoder 33, causing Viterbi decoding and CRC checks to be performed, and also detects the data rate of the received data based on the maximum path metric, minimum path metric and zero-state path metric, as well as the CRC check result from the CRC decoder 33.
Next, the operation of the reception device 3 which detects the data rate of received data is explained, referring to the flowchart of FIG. 3. Here it is assumed that, as in FIG. 2, there exist four data rates Ri (i=1, 2, 3, 4).
In step S1, the data rate detection portion 34 sets the initial values of the internal counter i to 1, of the register Smin to a predetermined value D, and of the register Tr to 0.
In step S2, the data rate detection portion 34 controls the Viterbi decoding portion 32 to compute the maximum path matrix, minimum path metric, and zero-state path metric from the leading bit S up to the tail bit nend for the data rate Ri identified using the value of the counter i.
By this means, the Viterbi decoding portion 32 executes so-called ACS (Add-Compare-Select) processing to add, compare, and select values, and computes values of the maximum path metric, minimum path metric, and zero-state path metric. The Viterbi decoding portion 32 supplies the computed data to the data rate detection portion 34.
The reception device 3 (data rate detection portion 34) identifies in advance the possible data rates Ri, and can identify the data rate Ri based on the value of the counter i.
In this example, when the value of the counter i is 1, 2, 3, or 4 (the maximum value) (i=1, 2, 3, 4), the data rates R1, R2, R3, R4 are respectively identified, and the maximum path metric, minimum path metric, and zero-state path metric from the leading bit S to the E1st bit ((a) in FIG. 2), E2nd bit ((b) in FIG. 2), E3rd bit ((c) in FIG. 2), or E4th bit ((d) in FIG. 2) are computed.
Next, in step S3 the data rate detection portion 34 employs equation (1) to compute the S value based on the values for the maximum path metric, minimum path metric, and zero-state path metric supplied by the Viterbi decoding portion 32 in step S2.S value=10 Log((a0−amin)/(amax−amin))   (1)
In the equation, amax is the maximum path metric, amin is the minimum path metric, and a0 is the zero-state path metric. The maximum value of S is 0, and the minimum value is negative infinity.
In step S4, the data rate detection portion 34 judges whether the value of S computed in step S3 is or is not less than or equal to the threshold D.
When the data rate Ri identified through the value of the counter i is the true data rate of the received data, the zero-state path metric calculated by the Viterbi decoding portion 32 is a sufficiently small value, so that the value of S indicated by equation (1) is a small value. If on the other hand the data rate Ri is not the true data rate of the received data, the zero-state path metric calculated will not be a value that is sufficiently small, so that the value of S will not be a small value. In other words, by judging whether or not the calculated value of S is less than or equal to the threshold D, it is possible to decide whether the data rate Ri identified using the value of the counter i can be regarded as the true data rate of the received data (whether it is possible that the data rate is the true data rate).
The threshold D is a comparatively large value, so that the S value for the true data rate is not judged to be larger than the threshold D.
In step S4, when the S value is judged to be equal to or less than the threshold D, that is, when the data rate Ri identified from the value of the counter i can be considered to be the true data rate for the received data (when there is the possibility that the data rate is the true data rate), processing proceeds to step S5.
In step S5, the data rate detection portion 34 controls the Viterbi decoding portion 32 to cause execution of traceback processing, and generates the data stream up to the tail bit nend for the data rate Ri identified by the value of the counter i (for example, if the value of the counter i is 1, the E1st bit). Further, in step S6, the data rate detection portion 34 controls the CRC decoder 33 to cause a CRC check of the data thus generated to be performed.
By this means, the Viterbi decoding portion 32 generates the data stream from the leading bit S to the tail bit nend for the data rate Ri, and supplies the data stream to the CRC decoder 33.
The CRC decoder 33 divides the decoded data supplied by the Viterbi decoding portion 32 (the decoded data from the leading data bit S to the tail bit nend for the data rate Ri) by a generator polynomial, and determines the remainder.
When the data rate Ri identified by the value of the counter i is the true data rate of the received data, there is a strong possibility that the remainder thus determined is 0; and when the data rate Ri is not the true data rate of the received data, there is a strong possibility that the remainder is not 0.
The CRC decoder 33 notifies the data rate detection portion 34 of the remainder thus determined, as the CRC calculation result.
In step S7, the data rate detection portion 34 judges whether or not an error exists in the received data, based on the CRC calculation result from the CRC decoder 33. That is, a judgment is made as to whether there exists an error in the received data, based on CRC calculation results for the case in which the data rate of the received data is the data rate Ri indicated by the value of the counter i at that time. If the CRC calculation result is not 0 (if the data rate Ri is not the true data rate), it is judged that an error exists, and if the CRC calculation result is 0 (if there is the possibility that the data rate is the true data rate), it is judged that an error does not exist.
When in step S7 it is judged that an error does not exist, processing proceeds to step S8, and the data rate detection portion 34 judges whether or not the value S calculated in step S3 is equal to or less than the value of the register Smin. The value D is initially set as the register Smin, so that an S value initially resulting in a “YES” judgment in step S4 will of course be equal to or less than the value of the register Smin.
In step S8, when the value of S is judged to be equal to or less than the value of the register Smin, processing proceeds to step S9, and the data rate detection portion 34 replaces the value of the register Smin with the currently calculated value of S. In other words, the judgment of step S8 is a judgment of whether the currently calculated value of S is the smallest among the values of S calculated thus far.
The data rate detection portion 34 also replaces the value of the register Tr with the current value of the counter i.
When in step S4 it is judged that the value of S is not less than or equal to the threshold D, or when in step S7 an error is judged to exist, or when in step S8 the value of S is judged not to be less than or equal to the value of the register Smin, or when in step S9 the values of the register Smin and of the register Tr are interchanged, processing proceeds to step S10.
In step S10, the data rate detection portion 34 judges whether the value of the counter i is the maximum value (4), and if judged not to be the maximum value, processing proceeds to step S11, the value of the counter i is incremented by 1, processing returns to step S2, and subsequent processing is executed.
When in step S10 the value of the counter i is judged to be the maximum value, processing proceeds to step S12, and the data rate detection portion 34 detects the data rate Ri identified by the value of the register Tr as the true data rate of the received data. The data rate detection portion 34 controls the Viterbi decoding portion 32 to cause decoded data to be output at the detected data rate Ri. Then, processing ends.
In Japanese Patent Laid-open No. 2002-76923, the data rate detection processing heretofore explained is described.
In this way, detection of the rate of received data is performed when the rate is variable; in this case, if the above-described equation (1) is used to compute the value of S, because computations employ logarithms and division, the volume of calculations is large, and when for example implemented in hardware, there is the problem that the scale of circuitry and power consumption both become large.